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low power, rail-to-rail output, precision jfet amplifiers data sheet ad8641 / ad8642 / ad8643 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2011 analog devices, inc. all rights reserved. features low supply current: 250 a max very low input bias current: 1 pa max low offset voltage: 750 v max single-supply operation: 5 v to 26 v dual-supply operation: 2.5 v to 13 v rail-to-rail output unity-gain stable no phase reversal sc70 package applications line-/battery-powered instruments photodiode amplifiers precision current sensing medical instrumentation industrial controls precision filters portable audio ate general description the ad8641/ad8642/ad8643 are low power, precision jfet input amplifiers featuring extremely low input bias current and rail-to-rail output. the ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables designers to buffer cmos dacs, asics, and other wide output swing devices in single-supply systems. the outputs remain stable with capacitive loads of more than 500 pf. the ad8641/ad8642/ad8643 are suitable for applications utilizing multichannel boards that require low power to manage heat. other applications include photodiodes, ate reference level drivers, battery management, and industrial controls. the ad8641/ad8642/ad8643 are fully specified over the extended industrial temperature range of C40c to +125c. the ad8641 is available in 5-lead sc70 and 8-lead soic lead-free packages. the ad8642 is available in 8-lead msop and 8-lead soic lead-free packages. the ad8643 is available in 14-lead soic and 16-lead, 3 mm 3 mm, lfcsp lead-free packages. pin configurations out 1 +in 3 vee 2 vcc 5 ?in 4 ad8641 top view (not to scale) 05072-101 figure 1. 5-lead sc70 (ks-5) nc 1 ?in 2 +in 3 vee 4 nc 8 vcc 7 out 6 nc 5 ad8641 top view (not to scale) 05072-102 nc = no connect figure 2. 8-lead soic (r-8) out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ad8642 top view (not to scale) 05072-105 figure 3. 8-lead soic (r-8) out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ad8642 top view (not to scale) 05072-064 figure 4. 8-lead msop (rm-8) 05072-103 out a 1 out d 14 ?in a 2 ?in d 13 +in a 3 +in d 12 v+ 4 v? 11 +in b 5 +in c 10 ?in b 6 ?in c 9 out b 7 out c 8 top view (not to scale) ad8643 figure 5. 14-lead soic (r-14) 05072-104 12 11 10 9 +in c v? +in d ?in d 1 ?in a 2 3 5 ?in b out b out c ?in c 6 7 8 4 +in b v+ +in a 16 15 14 13 ad8643 top view pin 1 indicator nc out a out d nc notes 1. nc = no connect. 2. exposed pad should be connected to v+. figure 6. 16-lead lfcsp (cp-16) (not drawn to scale)
ad8641/ad8642/ad8643 data sheet rev. e | page 2 of 16 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? pin configurations ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? electrical characteristics............................................................. 3 ? absolute maximum ratings ............................................................5 ? thermal resistance .......................................................................5 ? esd caution...................................................................................5 ? typical performance characteristics ..............................................6 ? outline dimensions ....................................................................... 13 ? ordering guide .......................................................................... 15 ? revision history 9/11rev. d to rev. e changes to thermal resistance section........................................ 5 7/11rev. c to rev. d changes to figure 6.......................................................................... 1 11/10rev. b to rev. c changes to figure 6.......................................................................... 1 added thermal resistance section and table 4 .......................... 5 updated outline dimensions ....................................................... 13 changes to ordering guide .......................................................... 15 4/05rev. a to rev. b added ad8643 ...................................................................universal added 14-lead soic .........................................................universal added 16-lead lfcsp.......................................................universal updated outline dimensions ....................................................... 13 changes to ordering guide .......................................................... 14 3/05rev. 0 to rev. a added ad8642 ...................................................................universal changes to general description .....................................................1 added figure 3 and figure 4............................................................1 changes to specifications.................................................................3 changes to absolute maximum ratings........................................5 changes to figure 22.........................................................................8 changes to figure 23.........................................................................9 changes to figure 41...................................................................... 12 updated outline dimensions....................................................... 13 changes to ordering guide .......................................................... 14 10/04initial version: revision 0
data sheet ad8641/ad8642/ad8643 rev. e | page 3 of 16 specifications electrical characteristics v s = 5.0 v, v cm = 2.5 v, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit input characteristics offset voltage v os 50 750 v ad8643 lfcsp only 1 mv C40c < t a < +85c 1.5 mv +85c < t a < +125c, v cm = 1.5 v 1.6 mv input bias current i b 0.25 1 pa C40c < t a < +125c 180 pa input offset current i os 0.5 pa C40c < t a < +125c 60 pa input voltage range 0 3 v common-mode rejection ratio cmrr v cm = 0 v to 2.5 v 74 93 db large signal voltage gain a vo r l = 10 k, v o = 0.5 to 4.5 v 80 140 v/mv offset voltage drift ?v os /?t C40c < t a < +125c 2.5 v/c output characteristics output voltage high v oh 4.95 v i l = 1 ma, C40c to +125c 4.94 v output voltage low v ol 0.05 v i l = 1 ma, C40c to +125c 0.01 0.05 v output current i out 6 ma power supply power supply rejection ratio psrr v s = 5 v to 26 v 90 107 db supply current/amplifier i sy 195 250 a C40c < t a < +125c 270 a dynamic performance slew rate sr 2 v/s gain bandwidth product gbp ad8641, ad8642 3 mhz ad8643 2.5 mhz phase margin ? m 50 degrees noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 4.0 v p-p voltage noise density e n f = 1 khz 28.5 nv/hz current noise density i n f = 1 khz 0.5 fa/hz
ad8641/ad8642/ad8643 data sheet rev. e | page 4 of 16 v s = 13 v, v cm = 0 v, t a =25c, unless otherwise noted. table 2. parameter symbol conditions min typ max unit input characteristics offset voltage v os 70 750 v ad8643 lfcsp only 1 mv C40 < t a < +125c 1.5 mv input bias current i b 0.25 1 pa C40c < t a < +125c 260 pa input offset current i os 0.5 pa C40c < t a < +125c 65 pa input voltage range C13 +10 v common-mode rejection ratio cmrr v cm = ?13 v to +10 v 90 107 db large signal voltage gain a vo r l = 10 k, v o = C11 v to +11 v 215 290 v/mv offset voltage drift ?v os /?t C40c < t a < +125c 2.5 v/c output characteristics output voltage high v oh +12.95 v i l = 1 ma, C40c to +125c +12.94 v output voltage low v ol C12.95 v i l = 1 ma, C40c to +125c C12.94 v output current i out 12 ma power supply power supply rejection ratio psrr v s = 2.5 v to 13 v 90 107 db supply current/amplifier i sy 200 290 a C40c < t a < +125c 330 a dynamic performance slew rate sr 3 v/s gain bandwidth product gbp 3.5 mhz phase margin ? m 60 degrees noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 4.2 v p-p voltage noise density e n f = 1 khz 27.5 nv/hz current noise density i n f = 1 khz 0.5 fa/hz
data sheet ad8641/ad8642/ad8643 rev. e | page 5 of 16 absolute maximum ratings thermal resistance absolute maximum ratings apply at 25c, unless otherwise noted. table 3. parameter rating supply voltage 27.3 v input voltage vs? to vs+ differential input voltage supply voltage output short-circuit duration indefinite storage temperature range ks-5, r-8, rm-8, r-14, cp-16 packages ?65c to +150c operating temperature range ?40c to +125c junction temperature range ks-5, r-8, rm-8, r-14, cp-16 packages ?65c to +150c lead temperature (soldering, 60 sec) 300c ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. this was measured using a standard 4-layer board. for the lfcsp package, solder the exposed pad to a copper plane, which should be connected to v+. table 4. package type ja jc unit 5-lead sc70 (ks) 430 149 c/w 8-lead soic (r) 121 43 c/w 8-lead msop (rm) 142 45 c/w 14-lead soic (r) 110 36 c/w 16-lead lfcsp (cp) 81 16 c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad8641/ad8642/ad8643 data sheet rev. e | page 6 of 16 typical performance characteristics 0 10 20 30 40 50 60 70 frequency ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 ?0.35 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 v os (mv) 05072-002 80 v sy = 13v figure 7. input offset voltage number of amplifiers offset voltage ( v/ c) 05072-003 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 16 14 12 10 8 6 4 2 0 v sy = 13v figure 8. offset voltage drift 0 10 20 30 40 50 60 70 frequency ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 ?0.35 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 v os (mv) 05072-004 v sy = 2.5v figure 9. input offset voltage number of amplifiers t c v os ( v/ c) 05072-005 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 0 2 4 6 8 10 12 14 16 18 20 v sy = 5v v cm = 1.5v figure 10. offset voltage drift ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 input bias (pa) ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 1 3 5 7 9 11 13 15 v cm (v) 05072-006 v sy = 13v t a = 25c figure 11. input bias current vs. v cm ? 0.4 ? 0.3 ? 0.2 ? 0.1 0 0.1 input bias (pa) 0.2 0.3 0.4 ?15.0 ?12.5 ?10.0 ?7.5 ?5.0 ?2.5 0 2.5 5.0 7.5 10.0 12.5 15.0 v cm (v) 05072-007 v sy = 13v t a = 25c 0.5 ? 0.5 figure 12. input bias current vs. v cm
data sheet ad8641/ad8642/ad8643 rev. e | page 7 of 16 input bias current (pa) 0.1 1 10 100 1000 50 75 0 25 100 125 150 temperature ( c) 05072-008 v sy = 13v figure 13. input bias current vs. temperature ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 input bias (pa) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 v cm (v) 05072-009 v sy = +5v or 5v figure 14. input bias current vs. v cm v os ( v) ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 1 3 5 7 9 11 13 15 v cm (v) 05072-010 0 ?100 0 200 600 800 1000 400 100 500 700 900 300 v sy = 13v figure 15. input offset voltage vs. v cm ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 500 v os ( v) 1.0 1.5 0 0.5 2.0 2.5 v cm (v) 05072-011 v sy = 5v figure 16. input offset voltage vs. v cm open-loop gain (v/v) 10k 1m 100k 10m load resistance (k ) 0.1 10 1 100 05072-012 v sy = 13v v sy = 2.5v figure 17. open-loop gain vs. load resistance a vo (v/mv) 1 100 10 1000 ?50 ?30 ?10 10 30 50 70 90 110 130 150 temperature ( c) 05072-013 a. v sy = 13v, v o = 11v, r l = 10k b. v sy = 13v, v o = 11v, r l = 2k c. v sy = +5v, v o = +0.5v/+4.5v, r l = 10k d. v sy = +5v, v o = +0.5v/+4.5v, r l = 2k e. v sy = +5v, v o = +0.5v/+4.5v, r l = 600 a b c d e figure 18. open-loop gain vs. temperature
ad8641/ad8642/ad8643 data sheet rev. e | page 8 of 16 ?600 ?400 ?200 ?300 ?500 0 ?100 offset voltage ( v) 200 100 400 300 600 500 ?5 0 ?15 ?10 5 10 15 output voltage (v) 05072-014 10k 1k 100k v sy = 13v figure 19. input error voltage vs. output voltage for resistive loads ?350 ?250 ?150 ?200 ?300 ?50 ?100 input voltage ( v) 50 0 150 100 250 200 0 50 100 150 200 250 300 350 output voltage from supply rail (mv) 05072-015 r l = 1k pos rail neg rail r l = 10k r l = 2k r l = 100k r l = 100k r l = 10k r l = 1k r l = 2k v sy = 5v figure 20. input error voltage vs. output voltage within 300 mv of supply rails 0 100 200 300 400 500 i sy ( a) 600 700 800 4 8 12 16 20 24 28 v sy (v) 05072-016 +25c ?55c +125c figure 21. quiescent current vs. supply voltage at different temperatures saturation voltage (mv) 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 load current (ma) 05072-017 ? v sy ? v ol v sy ? v oh v sy = 13v figure 22. output saturation voltage vs. load current saturation voltage (mv) 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 load current (ma) 05072-018 v ol v sy ?v oh v sy =5v figure 23. output saturation voltage vs. load current ?30 ?135 ?90 ?45 0 45 90 135 180 225 270 315 ?20 ?10 0 10 20 30 40 50 60 70 10k 100k 1m 10m phase (degrees) gain phase v sy = 13v r l = 2k c l = 40pf gain (db) frequency (hz) 05072-019 figure 24. open-loop gain and phase margin vs. frequency
data sheet ad8641/ad8642/ad8643 rev. e | page 9 of 16 ?30 ?135 ?90 ?45 0 45 90 135 180 225 270 315 ?20 ?10 0 10 20 30 40 50 60 70 10k 100k 1m 10m phase (degrees) gain phase gain (db) frequency (hz) 05072-020 v sy = 5v r l = 2k c l = 40pf figure 25. open-loop gain and phase margin vs. frequency frequency (hz) ?30 ?20 ?10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 10m gain (db) v sy = 13v r l = 2k c l = 40pf g = +100 g = +1 g = +10 05072-021 figure 26. closed-loop gain vs. frequency frequency (hz) ?30 ?20 ?10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 10m gain (db) g = +100 g = +1 g = +10 05072-022 v sy = 5v r l = 2k c l = 40pf figure 27. closed-loop gain vs. frequency ?60 ?40 ?20 0 20 40 60 80 100 120 140 1k 10k 100k 1m 10m frequency (hz) cmrr (db) 05072-023 v sy = 13v figure 28. cmrr vs. frequency ?60 ?40 ?20 0 20 40 60 80 100 120 140 1k 10k 100k 1m 10m frequency (hz) cmrr (db) 05072-024 v sy =5v figure 29. cmrr vs. frequency ?60 ?40 ?20 0 20 40 60 80 100 120 140 1k 10k 100k 1m 10m frequency (hz) psrr (db) 05072-025 +psrr ?psrr v sy = 13v figure 30. psrr vs. frequency
ad8641/ad8642/ad8643 data sheet rev. e | page 10 of 16 ?60 ?40 ?20 0 20 40 60 80 100 120 140 1k 10k 100k 1m 10m frequency (hz) psrr (db) 05072-026 v sy =5v +psrr ?psrr figure 31. psrr vs. frequency 0.01 0.1 1 10 100 1000 z out ( ) 1k 10k 100k 1m 10m 100m frequency (hz) 05072-027 g = +100 g = +10 g = +1 v sy = 13v figure 32. output im pedance vs. frequency 0.01 0.1 1 10 100 1000 z out ( ) 1k 10k 100k 1m 10m 100m frequency (hz) 05072-028 g = +100 g = +10 g = +1 v sy =5v figure 33. output im pedance vs. frequency ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 input bias (pa) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 v cm (v) 05072-009 05072-029 ch1 10.0v ch2 10.0v m400 s a ch1 1.00v 1 t 0.00000s 2 v in v out t v sy = 13v figure 34. no phase reversal ?15 ?10 ?5 0 5 10 15 output swing (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 settling time ( s) 05072-030 v s = 13v gain = +5 ts ? (0.1%) ts ? (1%) ts + (0.1%) ts + (1%) figure 35. output swing and error vs. settling time 0 10 20 30 40 50 60 70 overshoot (%) capacitance (pf) 1 100 10 1000 05072-031 os+ os? v s = 13v r l = 10k v in = 100mv p-p a v = +1 figure 36. small signal overshoot vs. load capacitance
data sheet ad8641/ad8642/ad8643 rev. e | page 11 of 16 0 10 20 30 40 50 60 70 overshoot (%) capacitance (pf) 1 100 10 1000 05072-032 os+ os? v s = 2.5v r l = 10k v in = 100mv p-p a v = +1 figure 37. small signal overshoot vs. load capacitance ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 input bias (pa) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 v cm (v) 05072-009 05072-033 ch1 1.00v m1.00s a ch1 ?20.0v 1 v s = 13v g = +1m ch1 p-p = 4.26v figure 38. 0.1 hz to 10 hz noise ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 input bias (pa) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 v cm (v) 0 5072-009 05072-034 ch1 1.00v m1.00s a ch1 ?20.0v 1 v s = 2.5v g = +1m ch1 p-p = 4.06v figure 39. 0.1 hz to 10 hz noise voltage noise density (nv/ hz) 1 10 100 1k frequency (hz) 10 1k 100 10k 05072-035 v sy = 13v figure 40. voltage noise density voltage noise density (nv/ hz) 1 10 100 1k frequency (hz) 10 1k 100 10k 05072-036 v sy = 5v figure 41. voltage noise density 0.000001 0.00001 0.0001 0.001 1k 100 12 thd + noise (%) frequency (hz) 05072-037 0.004 0 k 1v p-p input 2v p-p input 4v p-p input 8v p-p input v sy = 13v load = 100k gain = +1 10k figure 42. total harmonic distortion + noise vs. frequency
ad8641/ad8642/ad8643 data sheet rev. e | page 12 of 16 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 (db) 20 100 1k 10k 100k frequency (hz) 05072-041 ? + v in 2k ? + 2k 2k 20k v in = 18v p-p v in = 4.5v p-p v in = 9v p-p figure 43. channel separation
data sheet ad8641/ad8642/ad8643 rev. e | page 13 of 16 outline dimensions compliant to jedec standards mo-203-aa 1.00 0.90 0.70 0.46 0.36 0.26 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 072809-a 0.10 max 1.10 0.80 0.40 0.10 0.22 0.08 3 12 4 5 0.65 bsc coplanarity 0.10 seating plane 0.30 0.15 figure 44. 5-lead thin shrink small outline transistor package [sc70] (ks-5) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 45. 8-lead standard small outline package [soic_n] (r-8) dimensions shown in millimeters and (inches)
ad8641/ad8642/ad8643 data sheet rev. e | page 14 of 16 compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 46. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ab 060606-a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 45 figure 47. 14-lead standard small outline package [soic_n] (r-14) dimensions shown in millimeters and (inches) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. 1 0.50 bsc 0.60 max p i n 1 i n d i c a t o r 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad bottom view for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 07-17-2008-a figure 48. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-3) dimensions shown in millimeters
data sheet ad8641/ad8642/ad8643 rev. e | page 15 of 16 ordering guide model 1 temperature range package description package option branding ad8641aksz-r2 ?40c to +125c 5-lead sc70 ks-5 a07 AD8641AKSZ-REEL7 ?40c to +125c 5-lead sc70 ks-5 a07 AD8641AKSZ-REEL ?40c to +125c 5-lead sc70 ks-5 a07 ad8641arz ?40c to +125c 8-lead soic_n r-8 ad8641arz-reel7 ?40c to +125c 8-lead soic_n r-8 ad8641arz-reel ?40c to +125c 8-lead soic_n r-8 ad8642armz ?40c to +125c 8-lead msop rm-8 a0a ad8642armz-reel ?40c to +125c 8-lead msop rm-8 a0a ad8642arz ?40c to +125c 8-lead soic_n r-8 ad8642arz-reel7 ?40c to +125c 8-lead soic_n r-8 ad8642arz-reel ?40c to +125c 8-lead soic_n r-8 ad8643arz ?40c to +125c 14-lead soic_n r-14 ad8643arz-reel7 ?40c to +125c 14-lead soic_n r-14 ad8643arz-reel ?40c to +125c 14-lead soic_n r-14 ad8643acpz-r2 ?40c to +125c 16-lead lfcsp_vq cp-16-3 aua ad8643acpz-reel7 ?40c to +125c 16-lead lfcsp_vq cp-16-3 aua ad8643acpz-reel ?40c to +125c 16-lead lfcsp_vq cp-16-3 aua 1 z = rohs compliant part.
ad8641/ad8642/ad8643 data sheet rev. e | page 16 of 16 notes ?2004C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05072-0-9/11(e)

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